Recent years have seen liquid crystal display devices which, as one type of flat display apparatus applicable in portable terminal device such as PDA's and mobile phones, have liquid crystal display panel driving circuits formed integrally with a glass substrate serving as an insulating substrate constituting part of the liquid crystal display panel.
FIG. 1 is a plan view of one such liquid crystal display device 1. The liquid crystal display device 1 has each of its pixels constituted by a liquid crystal cell, a polysilicon TFT (Thin Film Transistor) acting as the switching device of this liquid crystal cell, and an auxiliary capacitor. The pixels are disposed in a matrix to form a rectangular display unit 2. The liquid crystal display device 1 has horizontal driving circuits 3 and 4 formed parallel to the upper and the lower sides of the display unit 2 respectively, the two sides being located opposite to each other. A vertical driving circuit 5 is disposed parallel to one of the remaining two sides extending vertically.
The horizontal driving circuits 3 and 4 are provided to set color gradations for the odd-numbered and even-numbered columns of pixels in the display unit 2. More specifically, gradation data D1 and D2 for the odd-numbered and even-numbered columns are input to the liquid crystal display device 1 in a raster scan sequence through an input unit 6 disposed on the top of the device. In the horizontal driving circuits 3 and 4, sampling latches 3A and 4A each have a plurality of latching elements which correspond to the pixels in the line direction and which latch input image data cyclically. In this manner, the horizontal driving circuits 3 and 4 get the sampling latches 3A and 4A to hold temporarily the gradation data D1 and D2 on a line-by-line basis, the data being input in the raster scan sequence.
Second latches 3B and 4B are provided to further latch the latched results from the latching elements making up the sampling latches 3A and 4A, the second latching being done concurrently and in parallel at horizontal scanning intervals. The gradation data D1 and D2 are thus brought together on a line-by-line basis for output to level shifters 3C and 4C.
The level shifters 3C and 4C are provided to level-shift the gradation data D1 and D2 output concurrently and in parallel from the second latches 3B and 4B, in such a manner as to drive conductive (N-channel/P-channel) MOS (Metal Oxide Semiconductor) transistors that constitute digital-to-analog converters (DAC) 3D and 4D located downstream. The digital-to-analog converters 3D and 4D generate and output driving voltages corresponding to the gradation data D1 and D2. In the horizontal driving circuits 3 and 4, a plurality of driving voltages thus generated are supplied to the column lines of the display unit 2. This causes the odd-numbered and even-numbered columns to be set cyclically to the driving voltages corresponding to the gradation data D1 and D2 for the vertically continuous pixels.
The vertical driving circuit 5 selects one by one the row lines of the display unit 2 in keeping with the driving voltages set on the column lines, thus activating the TFT's of the corresponding pixels. In this manner, the liquid crystal display device 1 displays desired pictures using the gradation data D1 and D2.
The above type of liquid crystal display device has come to adopt the digital-to-analog converters 3A and 4D, as disclosed illustratively in Japanese Patent Laid-open No. 2000-242209, in order to generate driving voltages by selecting a plurality of reference voltages in accordance with the gradations derived from the gradation data D1 and D2 (this setup is called the reference voltage selection type). In this case, as shown in FIG. 2 in comparison with FIG. 1, a reference voltage generation circuit 7 for generating multiple reference voltages is located parallel to the remaining vertical side of the display unit 2 and equidistant from the horizontal driving circuits 3 and 4. Thus positioned, the reference voltage generation circuit 7 supplies the reference voltages to the two horizontal driving circuits 3 and 4. This layout is intended to suppress variations in the reference voltages for the odd-numbered and even-numbered columns, thereby effectively bypassing vertical streaks that may occur on the display screen due to reference voltage fluctuations.
FIG. 3 is a connection diagram showing the digital-to-analog converters 3D and 4D of the reference voltage selection type. In the digital-to-analog converters 3D and 4D, a plurality of series circuits C0 through C63 are provided corresponding to the gradations in effect, each series circuit being composed of switching circuits turned on and off depending on the logical values of bits b0 through b5 stemming from the gradation data D1 and D2. One end of the series circuits C0 through C63 is supplied with reference voltages V0 through V63 respectively. The other end of the series circuits C0 through C63 is connected to a column line OUT. FIG. 3 shows a setup where the gradation data D1 and D2 occur in increments of six bits. The switching circuits are formed by conductive (N-channel/P-channel) MOS transistors. The N and P channels are disposed in such a manner that the switching circuits may select the reference voltages corresponding to the values of the gradation data D1. The digital-to-analog converters 3D and 4D are thus arranged to select and output the reference voltages V0 through V63 in keeping with the gradation data D1 and D2. FIG. 4 is a connection diagram showing switches replacing the transistors.
In the digital-to-analog converters 3D and 4D of the above-described structure, the other end of the series circuits C0 through C63 for selecting the reference voltages V0 through V63 is connected to the column line OUT of the display unit 2. The column line OUT is extended in the direction perpendicular to the sides along which the horizontal driving circuits 3 and 4 are disposed. The layout forms a block B (FIG. 4) of the series circuits C0 through C63 which are arranged in the vertical direction and which correspond to one pixel. Such blocks B are disposed continuously in the horizontal direction parallel to those sides of the display unit 2 along which the horizontal driving circuits 3 and 4 are located. In this layout, the reference voltages V0 through V63 are set for common use by the horizontally continuous blocks B by way of horizontally extended lines. The liquid crystal display device 1 is arranged in this manner to make the most of limited space on the substrate.
The odd-numbered and even-numbered columns are formed by the pixels for red, blue and green colors laid out one after another. In this setup, the horizontally continuous blocks B are assigned cyclically to the driving of the red, blue and green pixels. The blocks B are laid out at twice the repeating pitch P for the pixels.
If the series circuit blocks B are disposed in a manner corresponding to the repetitive pixels for the red, blue and green colors, if the blocks B are fed commonly with the reference voltages V0 through V63, and if there are N gradations provided by the reference voltages V0 through V63, then it is possible to give displays in N×N×N colors. In that case, the gradation data D1 and D2 corresponding to the reference voltages V0 through V63 permit displays in as many colors as 2 to the (3×n)th power where N=2n. It follows that if the gradation data D1 and D2 occur in increments of six bits, it is possible to provide displays in about 260,000 colors.
However, portable terminal apparatuses are generally not required to give displays in as many as 260,000 colors. Typically, the gradation data D1 and D2 are set to be furnished in increments of six bits for the green color and in increments of five bits for the red and blue colors. This gives 64×32×32 colors (approximately 65,000 colors).
That means the conventional liquid crystal display device 1 described above with reference to FIGS. 1 through 4 has excess transistors included in the blocks B for the red and blue colors in the digital-to-analog converters 3D and 4D. The extra transistors are bound to dissipate power wastefully.
Removing these superfluous transistors provides two major benefits: the area occupied by the framework structure of the display unit 2 containing the excess transistors is made smaller, and the electric power consumption of the device is reduced correspondingly.